EDN

Articulating Hierarchical Design for SOCs

Designers of system on a chip (SOCs) use many design methodologies, flows, and tools to achieve timing closure. The current physical synthesis tools attack the problem of block-level timing ...
Electronic Design

Synopsys Debuts DesignWare STAR Hierarchical System to Accelerate SoC Test

September 11, 2013. Synopsys Inc. has announced the availability of its DesignWare STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including ...
EDN

Hierarchical design methodology supports complex FPGAs

FPGA devices have grown to ASIC size and complexity, but traditional EDA tools and methodologies have failed to keep pace. Engineers designing high-end FPGAs are beginning to face the types of ...
Electronic Design

Hierarchy Spells Order For SoC Data-Management Tool

No longer must SoC designers struggle with data that's organized in a file-based fashion. Increasingly, system-on-a-chip (SoC) design is a discipline that requires its practitioners to look, at least ...
Semiconductor Engineering

Hierarchical LP Design

The rapidly shrinking process geometry is a double-edged sword. It allows unprecedented integration of circuits. But it also produces leakier transistors, which is one of the main reasons behind the ...
Semiconductor Engineering

Hierarchical DFT On A Flat Layout Design

The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules. Hierarchical DFT divides the design into smaller pieces, creates test ...